1. Field of the Invention
Implementations described herein relate generally to semiconductor devices, and, more particularly, to a memory device protection layer.
2. Description of Related Art
The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability, and increased manufacturing throughput. The reduction of design features below a critical dimension (CD) challenges the limitations of conventional methodologies.
For example, as memory devices are continuously scaled to smaller sizes, there is an ever greater demand to reduce the diffusion of dopants. However, the enhancement of diffusion due to oxidation-enhanced diffusion (OED) poses severe challenges to this goal. Another problem is the growth of a “bird's beak” in the source and/or drain regions of the memory devices. Such bird's beaks grow below the gates of the memory devices and take up valuable circuit real estate. Bird's beaks may also induce stress damage in memory devices due to a mismatch in thermal expansion properties between materials.
Still another problem is penetration of mobile ions during back end of line (BEOL) processing of memory devices. Mobile ions may penetrate the source and/or drain regions of the memory devices, where they may acquire an electron and deposit as a corresponding metal in the source and/or drain regions, destroying the memory devices. Furthermore, mobile ions may also support leakage currents between biased memory device features, which degrade memory device performance and ultimately may destroy the memory device by electrochemical processes, such as metal conductor dissolution.